`timescale 1ns / 1ps
module sim_alu;
  parameter size = 32;
  reg  [3:0] OP;
  reg  [size:1] A, B;
  wire [size:1] F;
  wire ZF, CF, OF, SF, PF;

  ALU alu (OP, A, B, F, ZF, CF, OF, SF, PF);

  initial begin
    OP = 4'b0000;  A = 32'h5555_5555; B = 32'h0F0F_0F0F; #10;
                                    A = 32'hFFFF_0000; B = 32'h0000_FFFF; #10;
#5;
    OP = 4'b0001; A = 32'hAAAA_AAAA; B = 32'h0F0F_0F0F; #10;
                                    A = 32'h1234_5678; B = 32'h8765_4321; #10;
 #5;
    OP = 4'b0010; A = 32'hFFFF_FFFF; B = 32'hFFFF_0000; #10;
                                    A = 32'h00FF_00FF; B = 32'hFF00_FF00; #10;
#5;
    OP = 4'b0011; A = 32'h0000_0000; B = 32'hFFFF_FFFF; #10;
                                     A = 32'hAAAAAAAA; B = 32'h5555_5555; #10;
#5;
    OP = 4'b0100; A = 32'h0000_0001; B = 32'h0000_0001; #10;
                                    A = 32'h7FFF_FFFF; B = 32'h0000_0001; #10;
#5;
    OP = 4'b0101; A = 32'h0000_0002; B = 32'h0000_0001; #10;
                  A = 32'h8000_0000; B = 32'h0000_0001; #10;
 #5;
    OP = 4'b0110; A = 32'h0000_0005; B = 32'h0000_0003; #10;
                                A = 32'h0000_0003; B = 32'h0000_0005; #10;
#5;
    OP = 4'b0111; A = 32'd1; B = 32'h8000_0001; #10;
                                 A = 32'd4; B = 32'h1234_5678; #10;
  end
endmodule